In the prior art, in order to prevent false triggering of the ESD clamp, the noise is modeled by voltage overshoots. For voltage overshoots, a Noise Voltage Buffer (NVB) is used as can be seen in FIG. 1. FIG. 1 shows a schematic block diagram of the prior art representing an ESD protection circuit 100 of an integrated circuit (IC). The ESD protection circuit 100 includes an ESD clamp, a SCR 102 coupled to a Node1 104 which represents a pad of the IC. The IC pad of Node1 104 may be an input pad, an output pad, or a supply pad. Node2 106 may be a ground or also an input/output pad. The triggering tap, G2 of the SCR 102 is coupled to Node3 108 which may be an input pad, an output pad or a supply pad. In this example of FIG. 1, Node1 104 represents an input pad, Node2 represents ground and Node3 108 represents a power supply. A Noise Voltage Buffer (NVB) 110 is coupled between the triggering tap G2 of the SCR 102 and Node3 108. A shunt resistor R1 112 is optionally coupled between the SCR 102 and the Node2 106.
During normal operation, Node3 108 is powered, however at Node1 104 the voltage is lower than the power supply, i.e. not enough voltage to conduct current between the anode and the grounded cathode. Thus, the SCR 102 is turned off. In order for SCR 102 to turn on there must be at least 0.7 volts between Node1 and G2 of the SCR 102. Because the input voltage, i.e. at Node1 104 is below the power supply, i.e. Node3 108, thus SCR 102 cannot trigger during normal operation. During ESD, the power supply at Node3 108 is essentially at 0 volts, however, the voltage at Node1 104 is high, i.e. at least 0.7 volts or higher, then there will be voltage over G2 anode junction, causing the SCR 102 to turn on or trigger. The ESD current will run through the SCR 102 from Node1 104 to Node2 106.
In a case scenario the input voltage at Node1 104 may become higher than the power supply, Node3 108 during normal operation. For example voltage at Node3 108 is 1.8 volts and voltage at Node1 102 is 2 volts or higher which can trigger the SCR 102 to turn on during normal operation. Normally the voltage at the input or output node 104 is limited below the power supply, but voltage overshoot (noise, spikes) can introduce these overvoltages. Thus, in this situation, SCR 102 is triggered not due to the ESD, but due to high voltage at the input pad, Node1 104. This is the false triggering of the SCR 102 which is not a desired application during normal operation. Thus, the NVB 110 will lower the voltage occurring between the anode and G2 by dividing the voltage in series. So, for example, the 0.7 volts at Node1, will be divided into 0.3 volts over the G2 anode junction and 0.3 volts over the NVB 110, thus limiting the voltage over the G2 anode junction. Therefore, NVB 110 prevents G2 from the triggering of the SCR 102 during normal operation, thus preventing that the voltage overshoot noise will trigger the SCR.
Although attempts have been made in the past to reduce the false triggering of the SCR by different circuit techniques, there still exist a danger for unwanted triggering of the device during normal supply line powered operation.